1-GHz and 2.8-GHz CMOS Injection-locked Ring Oscillator Prescalers
Rafael J. Betancourt-Zamora, Shwetabh Verma, Thomas H. Lee
Symposium on VLSI Circuits, Kyoto, Japan, June 14, 2001 (paper, slides PDF)

We implemented prescalers that can operate up to 2.8 GHz by exploiting the injection locking phenomena in differential CMOS ring oscillators. We tested a 5-stage, 1-GHz injection-locked modulo-8 prescaler fabricated in a 0.24-um CMOS technology that consumes 350 uW of power and occupies 0.012 mm2 of die area. The locking range is 20 MHz and the locked phase noise is -110 dBc/Hz @ 100 kHz. A 2.8-GHz, 3-stage, modulo-4 divider is also presented.

CMOS VCOs for Frequency Synthesis in Wireless Biotelemetry 
Rafael J. Betancourt-Zamora and Thomas H. Lee 
International Symposium on Low Power Electronics and Design, Monterey, California, August 10-12, 1998. (paper, poster PDF) 

The Hajimiri phase noise model was used to optimize a differential  ring VCO for minimum power consumption. We compare the phase noise performance of three buffer stages using clamped, symmetric and cross-coupled loads, respectively. We propose a cross-coupled buffer topology that achieves lower phase noise by exploiting symmetry. Measured phase noise for a 1.2mW, 150MHz VCO fabricated in 0.5um CMOS is -103.9dBc/Hz at 500KHz offset, showing good agreement with the theory.

Low Phase Noise CMOS Ring Oscillator VCOs for Frequency Synthesis  
Rafael J. Betancourt-Zamora and Thomas H. Lee 
2nd International Workshop on Design of Mixed-Mode Integrated Circuits, Guanajuato, Mexico, July 27-29, 1998, pp. 37-40. (paper, slides PDF)

We propose a methodology that uses a new phase noise model to trade-off phase noise and power dissipation in the design of ring oscillators suitable for frequency synthesis. We compare the theoretical phase noise performance of three buffer stages using clamped, symmetric and cross-coupled loads, respectively. We propose a cross-coupled buffer topology that achieves lower phase noise by exploiting symmetry. This achieved a 95% reduction in the 1/f3 corner frequency of the phase noise characteristic.

A Low Power Frequency Synthesizer for Wireless Biotelemetry 
Rafael J. Betancourt-Zamora  
33rd. International Telemetering Conference, Las Vegas, Nevada, October 27-30, 1997. (slides PDF) 

A system architecture based on a frequency-locked loop frequency synthesizer is presented, and a novel differential frequency discriminator that eliminates the need for a frequency divider is also proposed. A test chip was fabricated in a 0.5 um, 3V CMOS process.

Low Phase Noise CMOS Ring Oscillator VCOs for Frequency Synthesis  
Rafael J. Betancourt-Zamora and Thomas H. Lee 
2nd International Workshop on Design of Mixed-Mode Integrated Circuits, Guanajuato, Mexico, July 27-29, 1998, pp. 37-40. (paper, slides PDF) 

We propose a methodology that uses a new phase noise model to trade-off phase noise and power dissipation in the design of ring oscillators suitable for frequency synthesis. We compare the theoretical phase noise performance of three buffer stages using clamped, symmetric and cross-coupled loads, respectively. We propose a cross-coupled buffer topology that achieves lower phase noise by exploiting symmetry. This achieved a 20 times reduction in the 1/f³ corner frequency of the phase noise characteristic.

A 1.5 mW, 200 MHz CMOS VCO for Wireless Biotelemetry 
Rafael J. Betancourt-Zamora, Ali Hajimiri, and Thomas H. Lee 
First International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, Cancun, Mexico, July 28-30, 1997, pp. 72-74. (paper, slides PDF) 
 
Our goal is to build a low-power 174-216 MHz RF transmitter suitable for short range biosensor and implantable use. A system architecture based on a frequency-locked loop frequency synthesizer is presented, and a novel differential frequency discriminator that eliminates the need for a frequency divider is also proposed. The Hajimiri phase noise model was used to optimize the VCO for minimum power consumption. A test chip was fabricated in a 0.5 um, 3V CMOS process. Measured phase noise for a 1.5 mW, 200 MHz ring oscillator VCO is -80 dBc/Hz at 100 kHz offset, showing good agreement with the theory.

A High-speed GaAs Transversal Filter Circuit for Clutter Rejection Systems 
Spencer White and Rafael J. Betancourt-Zamora 
SPIE's Tech. Symp. Optical Eng. & Photonics in Aerospace Sensing, April 1990. (paper PDF) 

A high-speed GaAs Transversal Filter IC that has been designed at Hughes Aircraft Company and fabricated at AT&T Bell Laboratories is described. This circuit, which contains in excess of 41,000 transistors, implements a finite impulse response (FIR) filter for infrared data stream signal-to-noise ratio (SNR) enhancement in clutter rejection systems. The die is 9.1 mm on a side and dissipates 5.1 Watts. In addition This was implemented in a 1um GaAs HFET process with two layers of Ti/Pt/Au metallization.