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EXPERIENCE
2003 - Present Chabot College
Hayward, California
Engineering Instructor
Instruction for the full suite of lower division engineering courses needed by students to transfer to four-year institutions. Courses instructed include: Introduction to Engineering, Engineering Graphics, Plane Surveying, Static Force Mechanics, Circuit Analysis, Materials of Engineering. Coordination of the Chabot program with Industry, and Universities. Cirriculum development to ensure that program remains current and relevant.
2000 - 2003 Olympus-ITA
San Jose, California
Director System Design & Integration Engineering
Responsible for systems engineering as a part of product development, and for technical support of demo/applications development. Hardware design Leader for optical inspection products in the semiconductor and flat-panel industries. Responsibilities include mechanical & electrical hardware design, product development engineering, industry-standards compliance, developing strategic technical alliances, management of engineering projects, and customer engineering support activities in areas outside of inspection products.
1979 - 2000 Silicon Valley Group (Watkins-Johnson Co. until Jul99)
Scotts Valley, California
Director, Systems Engineering
Managed a group comprised of 22 engineers and technicians. Supervised 4 Managers. Set schedules and priorities for the development of Chemical Vapor Deposition (CVD) and Thermal Oxidation (HTO) machine tools used in the manufacture of Integrated circuits. Deveolped Human-Resource and Capital-Equipment Budgets. Represented the group before important customers and upper management.
Leader, New Product (APNext™) Development Team
Lead an interdisciplinary engineering team to design, develop, test, and manufacture the 3rd generation SVG/WJ Chemical Vapor Deposition (CVD) process equipment for semiconductor integrated circuit fabrication. The SVG/WJ APNext™ CVD system provides a solution for deposition of Poly-Metal-Dielectric (PMD), and Shallow Trench Isolation (STI) silica based thin films on 200 or 300 mm wafers.
Duties include: Creation of the program plan including team-member functions, schedule, budget, and Market Requirements Statement: Development of system architectures; presentation of preliminary designs to prospective American, Japanese , European, and Korean customers; final technical authority, ranging from the high level architectural concept, to writing of the detailed system design specification; design engineering of prototype lab facility; day-to-day direction of prototype unit (alpha-unit) construction; presentation of alpha-unit performance results to selected potential customers; negotiation of ß-site agreement with a major European IC manufacturer; assistance with preparation of promotional activities such as trade show attendance and brochure development; leadership of Technical/Schedule Risk-Reduction Task Teams; assessment of intellectual property issues, and writing of patent applications.
Senior Electrical Design Engineer
Responsible for design and analysis of primarily analog electronic circuits used to control WJ Chemical Vapor Deposition (CVD) process equipment for semiconductor integrated circuit fabrication. Duties include SPICE modeling for optimization of instrument-critical circuits.
Leader, New Product (WJ-1000) Development Team
Lead an interdisciplinary engineering team to design, develop, test, and manufacture the 2nd generation WJ Chemical Vapor Deposition (CVD) process equipment for semiconductor integrated circuit fabrication. The WJ-1000 CVD system provides a solution for deposition of Poly-Metal-Dielectric (PMD), and Inter-Metal-Dielectric (IMD) silica based thin films on 200 mm wafers. See Also http://www.avizatechnology.com/products/vapor.htm
Duties include: development of alternative system architectures; presentation of preliminary designs to prospective customers in the USA, Japan, and Korea; final technical authority, ranging from the high level architectural concept, to writing of the detailed system design specification; detail design engineering of the system exhaust, and prototype lab facility; day-to-day direction of prototype unit (alpha-unit) construction; direction of alpha-unit testing, and CVD process development; presentation of alpha-unit performance results to selected potential customers; negotiation of ß-site agreement with a major Japanese IC manufacturer; assistance with preparation of promotional activities such as trade show attendance and brochure development; budget and schedule responsibility.
Head, Flat Panel Deposition Equipment Engineering
Responsible for the operation of a seven person engineering group. Direct and supervise activities needed for design, manufacturing, and research and development engineering of Chemical Vapor Deposition (CVD) process equipment for glass coating applications. Glass coating CVD machine tools find application in the production of photovoltaic solar energy devices, and a variety of flat panel information displays such as those used on lap top computers.
Duties include development of strategic decisions such as new product development goals, improvement of customer satisfaction, general product and quality improvement, cost reduction, and R&D budgeting/goals. Duties also include extensive interaction with potential customers including proposal evaluation and quotation preparation, technical presentations, negotiations of requirements for potential products, problem solving after delivery of equipment.
Process Equipment Project Engineer
Responsible for R&D, design and manufacturing engineering of CVD systems, and conveyorized firing furnaces. Responsible for complete mechanical and control logic (electro-mechanical) design of CVD systems and conveyor furnaces. Duties also included evaluation of requests for proposals, cost estimation for proposed equipment, technical presentations to customers, field service engineering, technical support for the engineering group in fluid mechanics and heat transfer.
1980-1981 Cabrillo College
Aptos, CA
Engineering/Computer Science Instructor
Developed lesson plans, homework assignments, and grading procedures for the courses of Engineering & Society and FORTRAN. The Engineering & Society course examined the role and function of engineering in modern Society. The FORTRAN class was an intensive study of FORTRAN IV. Students with no computer experience became proficient in all fundamental FORTRAN techniques.
1978 - 1979 Lawrence Berkeley National Laboratory
Berkeley, CA
Research Technician
As part of the Building Envelopes Group, responsibilities included the design, construction, testing and operation of apparatus to evaluate the overall thermal performances of home fireplaces. Duties also included collection and evaluation of data on an actual installation at the Lawrence Berkeley Laboratory research house.
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PATENTS, PUBLICATIONS, AWARDS
• U.S. Patent Granted:, “Semiconductor wafer processing system with vertically-stacked process chambers and single-axis dual-wafer transfer system”, Patent No. 6,846,149. (2005)
• U.S. Patent Application: “System and method for preferential chemical vapor deposition”, Application No. 20040231588 (2004)
• U.S. Patent Granted: “Semiconductor Wafer Processing System With Vertically-Stacked Process Chambers And Single-Axis Dual-Wafer Transfer System”, Patent No.6,610,150 (2003)
• U.S. Patent Granted: "Method And System For In-Situ Cleaning Of Semiconductor Manufacturing Equipment Using Combination Chemistries”, Patent No. 6,544,345 (2003)
• B. Mayer, C. Collins, M. Walton, “Transient Analysis Of Carrier Gas Saturation In Liquid Source Vapor Generators” Journal of Vac. Sci. Tech. A, vol. 19, no.1 (2001)
• M. Refai, G. Aral, V. Kudriavtsev, B. Mayer, "Thermal Modeling for APCVD Furnace Calibration Using MATRIXx", Electrochemical Soc. Proc., vol. 97-9, pp. 308-316 (1997)
• B. Mayer, "Small Signal Analysis of Source Vapor Control Requirements for APCVD", IEEE Transactions on Semiconductor Manufacturing, vol. 9, no. 3 (Aug96)
• Winner, VLSI Technology “Best Product” Industry Award for the WJ-1000 Chemical Vapor Deposition Machine-Tool Product (1994)
• U.S. Patent Granted: "Method For Producing Highly Conductive And Transparent Films Of Tin And Fluorine Doped Indium Oxide By APCVD", Patent No. 5,122,391 (1992)
• B. Mayer, "Highly Conductive and Transparent Films of Tin and Fluorine Doped Indium Oxide by Produced by APCVD", Thin Solid Films, vol 221 (1992), 166
• R. Sonderegger, J. Kessel, B. Mayer, M. Modera, "In-Situ Measurements of Net Fireplace Efficiency Using Electric Co-Heating", Lawrence Berkeley Laboratory Report EEB-Env-79-2 (1979)
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SPECIAL SKILLS
• Familiar with IBM-PC software: Windows, AutoCAD, MS-Word, MS-Excel, MS-PowerPoint, MS-Project, MathCAD, Sigmaplot, SPICE
• Semiconductor Device Physics/Processing specialization for MSEE at Stanford University
• Extensive Program/Product-Development Management Skills and Experience
• Extensive Design & Analysis experience for High-Purity Fluid Flow Control-Systems
• Computer programming languages: Pascal, Fortran, Basic
• Trouble shooting experience using Mechanical instrumentation (calipers, thermocouples, Accelerometers) and electrical instrumentation (DMMs, Oscilloscopes)
• Well Developed Patent and Literature Search Capabilities
• Technical paper referee for Solar Energy Materials
• Extensive international travel experience
• Training in International SemaTech I300I Test Methodology
• Extensive Knowledge of SEMI S2/S8 Safety & Ergonomic Guidelines
PROFESSIONAL ASSOCIATIONS
• Member, Institute of Electrical and Electronics Engineers (IEEE)
• Member, American Society of Mechanical Engineers (ASME)
• Past Member, American Society of Heating, Air conditioning, and Refrigeration Engineers (ASHRAE)
• Past Member, Society for Information Display (SID)
• Past Member, National Society of Professional Engineers (NSPE)
REFERENCES
• Available upon request.
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