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Summary
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Over five years of hands-on experience designing both small and large-scale high-speed digital ASICs. Proficient in all aspects of ASIC design and verification. Strong problem solving and multi-tasking abilities. Fast learner with excellent communication, teamwork and leadership skills.
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Technical Skills |
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Verilog, VHDL, Synopsys VCS/Design Compiler/Primetime, Debussy, PERL, C, assembler, csh.
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Education
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University of South Alabama, Mobile, AL |
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Bachelor of Science - Electrical Engineering, June 1993
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Experience |
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Intel Corporation, Fremont, CA
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Sept 2004 - Present
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Verification Consultant
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Performed lab verification of 10 Gb SONET Framer/Mapper chip. Wrote C testbenches, performed lab measurements to verify hardware SDRAM interface.
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Ciena Corporation, Fremont, CA (Purchased Cyras Systems in March 2001)
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March 2001 - March 2002
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Senior ASIC Design Engineer
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Designed high-speed serial data receiver front ends for 160 Gbps SONET cross-connect switch. Major functional modules included complex pattern-recognition FSMs for data-word alignment and frame timing verification, clock-domain synchronization FIFOs, error detection / interrupt generation and uP interface registers. Coded all RTL modules and testbenches in Verilog. Synthesized all modules using Synopsys Design Compiler. Assisted chip verification and back-end teams to resolve last-minute feature additions and timing issues. Created Perl scripts for various netlist edits. (8+ Mgate, 0.18 micron, 155 MHz, Fujitsu).
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Cyras Systems, Fremont, CA
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February 1999 - March 2001
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ASIC Design Engineer
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Designed block and multi-chip Verilog testbenches for 40 Gbps SONET cross-connect switch ASIC. Created scripts and simulations for automated functional design verification. Provided fast design-change feedback required in a demanding start-up atmosphere. (1+ Mgate, 0.25 micron, 155 MHz LSI)
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Lockheed Martin Missiles and Space, Sunnyvale, CA
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August 1995 - February 1999
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Lead Design Engineer
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Specified, architected, designed and lab-tested a defense satellite atomic clock interface ASIC. Major functional blocks included triply-redundant/self-correcting real time clocks, timestamps, alarm clocks and fully programmable frequency dividers and pulse generators. Coded RTL, module and chip-level functional verification testbenches in VHDL. Performed lab testing to verify chip, board and system-level functionality. Debugged and repaired hardware evaluation boards. (150 kgate, 0.8 micron, 20 MHz, Honeywell).
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QMS, Incorporated, Mobile, AL
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September 1991 - August 1995
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Software Quality Engineer
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| - Designed laser print-engine simulator platforms for testing embedded laser-printer controller video output. Tasks included design of hardware and coding of low-level system software interfaces in C.
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| - Maintained and enhanced enterprise-class laser printer embedded system software across 6 product lines to resolve defects, add new functionality and create customer-specific feature sets.
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| - Led test teams of 3-5 engineers in laser printer final acceptance testing. Tasks included test plan development, defect resolution, verification, and scheduling of both human and equipment resources. |
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